Mathematical Analysis of Logical Masking Capability of Logic Gates
نویسندگان
چکیده
In this paper, logical masking capability of commonly used logic gates such as NOT, AND/NAND, OR/NOR, and XOR/XNOR, when subject to single/multiple input faults, are analyzed from a mathematical perspective. A new metric, called Gate Error Metric (GEM) is proposed to study the extent of output error in these gates when subject to potential input fault occurrences, where less value of GEM implies good logical masking. Generic GEM equations are deduced for n-input AND/NAND/OR/NOR, and XOR/XNOR gate types. The equations reveal that with an increase in fan-in output errors tend to reduce for all types of logic gates in general. In specific, AND/NAND/OR/NOR gates have similar GEM values and these are superior compared to the GEM values of XOR/XNOR gates. Key-Words: Logic gates; Logical masking; Modeling; Circuit analysis; Reliability; Fault tolerance
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